1. Field of the Invention
This invention relates to a ferroelectric memory device, having memory cells to store binary data as polarization states in a ferroelectric layer, and also relates to a method of manufacturing such a ferroelectric memory device.
2. Description of the Related Art
FeRAM (Ferroelectric Random Access Memory) devices are known as ferroelectric memories.
A ferroelectric layer in the FeRAM is formed from an oxide compound material. This oxide compound material undergoes a reduction reaction due to water (H2O) and hydrogen (H2) derived from this water which has irreversibly entered, for example, a CVD film formed in the vicinity of the ferroelectric layer. As a result of this reduction reaction, the polarization characteristics of the ferroelectric layer are degraded.
Japanese Patent Application Kokai (Laid-open) No. 2002-43541 discloses a configuration to prevent the diffusion into the ferroelectric layer of hydrogen arising from the process of formation of a passivation film. Specifically, a hydrogen diffusion prevention film of aluminum oxide (Al2O3) is provided on a metal wiring layer connected to the ferroelectric layer.
With the aim of reducing the effect of hydrogen occurring during formation of a passivation film, Japanese Patent Application Kokai No. 2003-100994 discloses a hydrogen diffusion prevention film of Si3N4 or SiON, having a film thickness of 10 nm to 200 nm and formed by reactive sputtering. The hydrogen diffusion prevention film is provided as a layer to cover the upper surface and side surfaces of the metal wiring.
According to Japanese Patent Applications Kokai No. 2002-43541 and No. 2003-100994, a hydrogen (or water) diffusion prevention film of aluminum oxide, Si3N4 or SiON is formed directly on the metal wiring.
When forming these prevention films, there is a possibility that a phenomenon called charge-up, in which the metal wiring is electrically charged, may occur. Details are described later.
The ALD (Atomic Layer Deposition) method is known as a method of film deposition which aims to resolve the drawbacks of conventional thermal CVD methods (see Japanese Patent Application Kokai No. 2004-023043).
As previously described, when a hydrogen (or water) diffusion prevention film is formed directly on metal wiring, charging-up of the metal wiring occurs. As a result, there is the possibility that the gate oxide film of transistors electrically connected to this metal wiring via buried contacts or other wiring structures connected to the metal wiring may be physically destroyed.
If the gate oxide film is destroyed, then logic circuit element functions such as control of memory cells are lost, and the device can no longer function properly as ferroelectric memory.
In general, the surface area of metal wiring formed in the logic circuit regions other than a memory cell array region is greater than the surface area (sum of the areas on the upper and side faces) of the first layer of metal wiring (first wiring layer) formed in the memory cell array region. The memory cell array region has a plurality of ferroelectric capacitors. Further, the wiring in the logic circuit region is directly connected to the gate electrodes of transistors. Hence destruction of the gate insulating films of the transistors due to charge-up occurs particularly easily in the logic circuit region.
In the conventional devices, a liner oxide film is formed prior to depositing a cover film, in order to prevent such charge-up. This liner oxide film is formed by for example the CVD method.
As described above, water is inevitably contained in a film formed by the CVD method. Moreover, this water may be decomposed in heat treatment to result in hydrogen.
Hence in order to prevent exposure of the ferroelectric layer to either water or to hydrogen, or to both, the prior art requires annealing at a temperature of approximately 400° C., with the purpose of dehydrating or dehydrogenizing the liner oxide film.
However, when annealing is performed under these conditions, there is the possibility of changes in the electrical characteristics of transistors formed in regions other than the memory cell array region in particular (e.g., in the logic circuit region). There is also the possibility of degradation of the ferroelectric layer characteristics.
Even if the liner insulating film is formed to a thickness of several hundred nanometers, the liner insulating film cannot prevent the above described problems.